Manual inspection of a complex printed circuit board is, in many cases, as expensive as its manufacture because of the labor intensive activity involved therein. Workers in the art have tried many approaches to solving this problem.
The automated detection of defective printed wire/circuit boards presents a complex problem. Early approaches to automated inspection of printed wire boards tried image comparison techniques employing a master printed circuit board, artwork, or a computer stored map for a master and comparing the PCB or PWB to the master to ascertain defects. However, this concept was not generally satisfactory, because of troublesome problems that were encountered in practice. For example, in such comparative analysis, the instantaneous area of the scanned image, or pixel-under-test, must match the corresponding area of the master. Thus, exact alignment is necessary at every point on the board. Shrinking or swelling of the board due to changes in temperature or humidity must be compensated for. The comparative analysis must also take into account normal and perfectly acceptable variations in the widths of the lines and the spaces of the pattern. As a result of these problems, it presently appears that the complexities inherent in the mechanization of this comparative technique renders such systems only marginally economical as a replacement for human inspection.
Bentley in "The Inspectron: An Automated Optical Printed Circuit Board (PCB) inspector", SPIE Vol. 201, Optical Pattern Recognition (1979), p 37-47, discloses a different approach based upon the logic inherent in PWB design. In the Bentley system, an automated printed wire circuit board inspection machine is employed which mechanically scans a hardwired distance-measuring sensor array of photodetectors located over the circuit board and utilizes logical decisions based upon the image pattern of the illuminated and nonilluminated detector to detect defective circuit boards.
Restrick in "An Automatic Printed Circuit Inspection System" SPIE Vol. 116, Solid State Imaging Devices (1977) describes a logic-type system (hereinafter the Restrick system) for printed circuit inspection which does not require total mechanical scanning of the sensor array over the circuit board. Instead, optical sensors scan a swath of a board as the sample board moves by on a support table.
In the Restrick system, three sensing units, each scanning a swath of the moving sample, are used. A lens associated with each sensing unit images a moving sample onto a 1728 element linear solid-state optical sensor.
Shift registers store individual line scans. A special purpose processor manipulates and temporarily stores the data. Digital logic to implement the error detecting algorithm is required for each sensing unit. Six consecutive scan lines are stored. The array scans in the Y-direction and the object is scanned mechanically in the X-direction. A bit stream is formed and stored in shift registers representing successive Y-positions for fixed X. Combinational logic applies line width/line spacing criteria to the contents of the registers. With each clock pulse a new area is stored in the shift registers and the error criteria applied.
U.S. patent application Ser. No. 521,069 filed Aug. 8, 1983 to MacFarlane discloses an improved printed circuit board defect detection system which is more flexible than the prior art Restrick or Bentley systems, in the sense that it can accommodate board to board line spacing and line width variations. It also is capable of detecting certain defects not otherwise detectable by the prior art systems, such as, the presence of unterminated lines.
In the MacFarlane system, pixel signals from each scanned line of a photodetector array, are accumulated in a plurality of shift registers, to form a moving "window" of matrix points. Each point in this matrix is in one of two possible logical states or polarities, depending on the instantaneous image, be it conductor or insulator, viewed by a corresponding photodetector element in the array.
Any of the pixel points in the matrix can be selected or addressed and a variety of logical principles applied thereto to determine if the image available in the matrix violates logical printed circuit board principles. Logic defects, such as (a) the presence of unterminated lines, (b) failure to meet minimum conductor width and spacing specifications, (c) the presence of holes in small areas of conductors or conductors in small areas of insulators, or (d) the presence of conductors having line widths in excess of specification can be detected.
A point select circuit capability permits the system to apply the defect detection logic to a plurality of inter-board line width and spacing sizes.
The MacFarlane system represents a considerable non-obvious advance over the prior art systems. Nevertheless, even greater flexibility is required to accommodate more recent printed circuit board designs. For example, newer printed circuit board designs employ conductor widths, which are non-uniform within a given board, i.e., intra-board variations. While the MacFarlane system is flexible enough to accommodate line-width and line-spacing variations from board-to-board, it cannot handle such intra-board line width variations.
Since the cost of a single automatic printed board defect sensor of the MacFarlane type is in excess of several hundred thousand dollars, its inability to detect defects in line width on printed circuit boards having more than one fixed line width represents a severe limitation upon its usefulness for more advanced PCB or PWB designs.
Additionally, the MacFarlane system does not have the capability of determining if a feature under inspection is centered. Hence, false defects may be indicated in the MacFarlane system if the feature is, in fact, not centered.
Also, in the MacFarlane system, there is no provision for determining the edge of a feature under inspection. Therefore, determination of feature size cannot be directly established by measuring the distance between edges.
Finally, in the MacFarlane system, the defect detection logic is somewhat limited in its accuracy for detection of complex circuit patterns. For example, features such as V-shaped conductor patterns, i.e., Vees, neck-downs, i.e.; narrowing down of conductors and stubs either cannot be detected or detected with a high degree of accuracy.